The present invention relates, in general, to the field of integrated circuit (“IC”) devices incorporating memory arrays. More particularly, the present invention relates to a reduced gate delay multiplexed interface and output buffer circuit for integrated circuit memory devices and those devices incorporating embedded random access memory arrays.
Many types of DRAM based devices, or integrated circuits including embedded memory arrays, are currently available including extended data out (“EDO”), synchronous DRAM (“SDRAM”), double data rate (“DDR”) DRAM and the like. Regardless of configuration, the primary purpose of the DRAM is to store data. Functionally, data may be written to the memory, read from it or periodically refreshed to maintain the integrity of the stored data. In current high density designs, each DRAM memory cell comprises a single pass transistor coupled to an associated capacitor that may be charged to store a value representative of either a logic level “1” or “0”. Data stored in these memory cells may be read out and written to them through columns of sense amplifiers coupled to complementary bit lines interconnecting rows of these cells.
Currently, output drivers are placed at or near the edge of the chip in integrated circuit memory devices or adjoining the edge of the macro in those devices including embedded memory arrays. This placement and the concomitant circuitry required can lead to overall performance problems in the “read” data path. For example, commodity DRAMs will typically have an output capacitance (“C”) specification of 50 pF (or 30 pF to 100 pF) so that placing an output driver remote from the edge of the chip will not significantly add to the load capacitance that the output buffer has to drive. However, the biggest problem is not with capacitance but resistance (“R”), where, for example, 100 ohms in series with this 50 pF load would place a 5.0 mSec lumped RC adder onto any access time. In previous generations of DRAMs, it was difficult to keep this resistance sufficiently low without placing the output buffer right at the output pad. For embedded DRAMs, the output load capacitance is generally less, with typical specifications on this parameter on the order of 0.2 pF.